1. Field of the Invention
The present invention relates to a device and method for testing an integrated circuit device, for detecting production failure of an integrated circuit (LSI).
2. Description of the Related Art
Detection of production failure of an integrated circuit (LSI) is performed such that a suitable signal value is applied to an input pin of the LSI by using a tester (ATE), and a signal value appearing at an output pin is compared with an expected result. A combination of the signal value of an input pin and the expected value of an output pin is referred to as a test pattern. A defect caused in a LSI by a production failure of the LSI is referred to as a fault, and in order to perform verification on all faults that may be caused in a LSI, a large number of test patterns are required. In addition, a ratio of faults which can be verified to faults which can be assumed to be in the LSI by a test pattern is referred to as a diagnosis rate (or detection rate), which is used as a measure when the quality of the test pattern is evaluated.
The method for creating a test pattern includes the following:                Random Test Generation (RTG)        Manual Test Generation        Automatic Test Pattern Generation (ATPG)        
Although the above described methods are combined to be used as required, the ATPG is used widely in order to obtain a high diagnosis rate. There are several methods in the ATPG, but those belonging to a path-sensitization algorithm are currently prevailing methods.
The path-sensitization algorithm consists of two fundamental steps of fault excitation and fault-effect propagation, for detecting a fault.
In the fault excitation, a value opposite to a fault value is set at a failure-assumed point. This makes a state value in a fault point different between a case where a fault is present and a normal case. This state is referred to that a failure is excited.
In addition, the fault-effect propagation is to propagate the effect of an excited failure to an observation point (external output). This makes all signal values on a path from a fault point to an observation point different between a normal time and a failure time. The path is referred to as a sensitized path. An example of the sensitized path is shown in FIG. 10. A thick solid line shows the sensitized path in a circuit shown in FIG. 10. The sensitized path also shows that a signal value for fault-excitation is set on a signal line a, and a signal value for fault-effect propagation is set on a signal line c and a signal line d.
In order to realize the fault excitation and the fault-effect propagation, it is necessary to set a desired signal value on a specified signal line. A signal line value in a circuit will be eventually resulted in a signal value of an external input which is a control point of a LSI. That is, in order to detect a fault, the ATPG creates a test pattern which consists of signal values of an external input for forming a sensitized path of the fault and expected values (signal values expected at a normal time) of an output to which the effect of the fault is propagated.
Several selections may take place in a process in which the ATPG creates a test pattern. For example, when a fault is excited by setting the output of a two-input AND gate to 0, either of the two inputs may be 0, so that either of the two inputs needs to be selected as the input to be set to 0. Also, in the case where there is a branch point of a signal line in the course of failure propagation, either one of the paths may be sensitized, so that a selection is also required in this case.
In a common ATPG, when several options exist, it is necessary to select one of them for the time being to advance processing. However, when the selection results in generation of a discrepancy in setting signal values or in a failure to sensitize the path, it is necessary to return to the processing of one previous step where the selection was performed and to select another option so as to advance processing. This is referred to as back-tracking.
In the case where a LSI includes a sequential circuit elements (flip-flop (F/F), latch and RAM), the complexity of the test pattern creation is drastically increased. Accordingly, there is performed a scan designing, in which a shift register (referred to as scan path) is formed by sequential circuit elements mainly comprising F/Fs in the LSI, so as to make a desired value shifted in at the time of test and values of the shift register read out to the outside after clock application. A technique referred to as the Deterministic Stored Pattern Test (DSPT), which is performed by storing in a tester a test pattern created by the ATPG, is widely employed for a circuit designed with the scan designing. FIG. 11 is a conceptual diagram of the DSPT. In the DSPT, a test pattern TP1 is shifted in a scan path SP provided in the LSI, so that a test pattern TP2 is shifted out.
However, since sequential circuit elements included in a LSI has recently increased drastically with high integration of the LSI, the DSPT which repeats the setting and reading operations for every test pattern for all sequential circuit elements constituting a scan path, causes to increase test time and data, so as to be difficult to be applied. Especially the shortage of memory capacity of a tester due to the increase in the amount of test data results in a memory expansion and an upgrade of the tester, thereby substantially increasing test costs.
In order to solve the problem, a Built-In Self Test (BIST) has come to be applied. FIG. 12 is a conceptual diagram of the BIST. In the BIST, a random pattern generated in a pseudo random number pattern generator 91 is applied to an internal circuit 90 of a LSI, and the output result is verified and stored in an output verification device 92. A linear feedback shift register (LFSR) is used, in many cases, for the pseudo random number pattern generator 91 and the output verification device 92, and the latter is in particular referred to as a multi-input signature register (MISR) as it compresses and stores the output result as a signature.
In the BIST, in which a pattern generator is installed in a LSI so that an input test pattern need not be stored in an external tester, and in which the test result is compressed by the MISR, the amount of data to be loaded in the tester can be drastically reduced. In the BIST, the number of scan paths is increased to enable the operation speed of shifting in and shifting out of a scan path to be increased, thereby reducing the test time.
Although the BIST is capable of improving the above described problem of the DSPT, it also has several disadvantages. In the BIST, since a pseudo random number pattern is used, a problem is involved in the test quality (diagnosis rate). In order to enhance the diagnosis rate, it is necessary to apply the DSPT as an additional test or to insert test points in the circuit inside the LSI so as to increase the controllability and observability.
Also, since the BIST is constructed such that output data are compressed and stored in the MIST, when an indeterminate state (X value) is taken in the MISR, the indeterminate value destroys the values in the MISR, thereby making it impossible to test. Generally, since sequential circuit elements including RAM in a LSI are in an indeterminate state when the power supply is turned on, it is necessary to initialize the sequential circuit elements or to devise a circuit for preventing the indeterminate state from being propagated to the MISR.
Further, it is necessary to devise in designing a bus to prevent a random pattern from causing a conflict and floating in the bus, which forces a strict design limitation on a designer when the BIST is applied to an actual circuit. In addition, a problem is also caused by an area overhead and performance degradation, which result from additional circuits and test points inserted for use in the BIST.
In order to solve the above described problems of the DSPT and BIST, a related test device and method are proposed in Japanese Patent Application Serial No. H12-372231, “Device and Method for Testing Integrated Circuit”, which enables a test time and the amount of test data to be reduced and the high quality of test to be attained.
FIG. 13 shows a block diagram of a circuit of a test device disclosed in the above described patent application. In the related art disclosed in the patent application, which is based on the BIST circuit, a pattern created by a pseudo random number pattern generator (LFSR) 93 is corrected by a pattern correction device 94 to be a pattern equivalent to that created by the ATPG, so as to be shifted in a scan path. After application of a test clock, the scan path output, of which indeterminate state values are subjected to mask-processing in an indeterminate state masking device 95, is compressed and stored in the MISR in an output verification device 96.
In general, the number of patterns created by the ATPG, values of which patterns are explicitly set to F/Fs, is very small compared with the total number of F/Fs (several %). In the technique disclosed in the above described patent application, only the values explicitly set to the F/Fs are provided for an external tester through a control signal 97, so as to enable a pseudo random number pattern to be corrected to be a high quality pattern equivalent to that created by the ATPG through the pattern correction device 94. Also, indeterminate state values which causes a design limitation in the BIST are blocked by the indeterminate state masking device 95 from being taken in the MISR, thereby substantially reducing a burden on a designer.
Thus, in the technique disclosed by the patent application, any test pattern generated by any kind of ATPG can be utilized. However, in order to substantially reduce test costs, such as the amount of test data and test time, the difference between a random pattern generated by the LFSR 93 provided inside the circuit and a pattern generated by the ATPG needs to be small.
Here, the ATPG determines values of several F/Fs necessary for several target failures and a number of remaining F/Fs are set to values created by the LFSR 93 provided in the circuit. This enables the difference between a random pattern and a test pattern to be made small. However, in the case where there are a number of target failures, or where sensitization is complicated, the number of F/Fs which need to be set by the ATPG is increased, as a result of which the test cost reduction rate is lowered.
In the related art disclosed in the above described patent application, F/F values set by the ATPG have no relation to F/F values set by the LFSR. F/F values set by the ATPG may be identical with half of F/F values set by the LFSR, but on the average, in the half of F/Fs set by the ATPG, additional patterns are created by the tester, which lowers the test cost reduction rate.
Accordingly it is an object of the present invention is to provide a test device and method for performing a test pattern creation so as to make the difference from a random number pattern generated by a pseudo random number pattern generator as small as possible, thereby increasing the test cost reduction rate.